`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/11/23 22:57:01
// Design Name: 
// Module Name: eqcmp
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

`include "funct.vh"
module store_t(
	input wire memwriteM,
	input wire [1:0] offset,
	input wire [2:0] storeM,
	input wire [31:0] oldwritedataM,
	output wire[31:0] writedataM,
	output wire [3:0] datamemEna,
	output wire addrstore


    );
	assign datamemEna = (storeM==`Sign_SB && offset==2'b00)?{3'b000,memwriteM}:
	(storeM==`Sign_SB && offset==2'b01)?{2'b00,memwriteM,1'b0}:
	(storeM==`Sign_SB && offset==2'b10)?{1'b0,memwriteM,2'b00}:
	(storeM==`Sign_SB && offset==2'b11)?{memwriteM,3'b000}:
	(storeM==`Sign_SH && offset[1]==1'b0 && offset[0]==0)?{2'b00,{2{memwriteM}}}:
	(storeM==`Sign_SH && offset[1]==1'b1 && offset[0]==0)?{{2{memwriteM}},2'b00}:
	(storeM==`Sign_SW && offset==2'b00)?{4{memwriteM}}:
	4'b0000;
	assign writedataM = (storeM==`Sign_SB)?{4{oldwritedataM[7:0]}}:
	(storeM==`Sign_SH)?{2{oldwritedataM[15:0]}}:
	(storeM==`Sign_SW)?oldwritedataM:
	32'b0;
	assign addrstore = (storeM==`Sign_SH && offset[0]!=1'b0)||(storeM==`Sign_SW && offset!=2'b00);

endmodule
